Georgia Tech Awarded IARPA Contract to Evaluate Emu Technology System

Traditionally, a rogues gallery is collection of criminals, maybe in a police lineup or Batman’s nemeses. However, the Georgia Institute of Technology is putting together a much different sort of collection of rogues.

The Center for Research into Novel Computing Hierarchies (CRNCH), led by Computer Science Professor Tom Conte, is spearheading the Rogues Gallery as one of its first initiatives since being founded in November 2016.  It will be a collection of some of the most unique computers in the field. These machines are so rare, only a few know how to program them, or they are so new, no one has programmed them. The goal is simple: to collect unusual hardware to make it accessible to the industry and academia.

With an Intelligence Advanced Research Projects Activity (IARPA) grant of $662,525, CRNCH researchers can finally purchase their first rogue, the Emu Chick.

This is a memory-centric architecture that employs threads — not processors — to move massive irregular data sets, effectively expediting data analysis workloads. The Chick could eventually be used to tackle fraud detection, genome sequencing for personalized medicine, real-time portfolio valuation and trading, and software development for larger Emu systems. But the machine is so new that its full capabilities aren’t known yet, making it an ideal Rogues Gallery resident.

Computational Science and Engineering senior research scientist Jason Riedy hopes to study the Chick’s performance, scalability, and programmablity with massive graphs and multilinear modeling for data analysis. He won’t be the only one testing the Chick’s capabilities.

The Rogues Gallery is designed to be open to all researchers, who could access the machine remotely if needed. Students will also have the chance to work on some of the most cutting edge machines, making them more competitive in the job market.

“The goal is to maintain Georgia Tech’s presence in novel and unusual architecture,” Riedy said.

CS research scientist Jeffrey Young and researchers at Georgia Tech Research Institute are working to set up a small cluster of Field Programmable Gate Array (FPGA) devices with 3-D stacked memory. These devices allow for programming custom, reconfigurable hardware, so that sparse linear solvers and graph analytic algorithms can be run at a faster rate. The team expects to have the Rogues Gallery open by late fall, and is exploring opportunities for other novel hardware related to embedded systems, neuromorphic, and quantum computing.

“When you have the hardware and expertise, people come to you,” Young said.